NVC VHDL Simulator 1.23.0

What's new in 1.23.0

This is a major new release with the following changes:
- Added basic support for System Verilog assignment pattern expressions.
- Added support for randomised signal initialisation using a bundled VHPI plugin. This is useful for finding reset issues, see the manual for details (from @Blebowski).
- Added support for System Verilog procedural assertions.
- Fixed an issue where VHPI could not iterate the constraints of objects declared with an unconstrained subtype (#1632).
- Fixed several cases where --preserve-case would cause incorrect behaviour (#1641).
- Added support for System Verilog sized casts (#1640).
- The value of 'instance_name for subprograms no longer includes spaces between parameters in the signature (#1648).
- Fixed a critical bug which could cause garbage collection to deadlock with background JIT threads (#1649).
- Fixed a bug where toggle coverage of a port could be incorrectly excluded as unreachable when --cover=exclude-unreachable was used, even though the port was actually driven (#1639).
- Several other minor bugs were resolved (#1638, #1636, #1579, #1647, #1658).
Special thank you to @bpadalino, @tmeissner, @Blebowski, @amb5l, @m42uko, @a-panella, @cmarqu, @albydnc, @johonkanen, @augustofg, @davidgussler, and Eltvor for sponsoring me!

Full release notes »